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NOVEMBER 2006
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
REV. 1.0.0
XRK39653 GENERAL DESCRIPTION
The XRK39653 is a low voltage high performance PLL based zero delay buffer/clock generator designed for high speed clock distribution applications. It provides 9 low skew, low jitter outputs ideal for networking, computing and telecom applications. The PLL based design allows the 9 outputs (8 clock outputs and 1 feedback output) to be phase aligned to the input reference clock. The outputs source LVCMOS compatible levels and can drive 50 transmission lines. If series termination is used, each output can drive up to 2 lines providing effectively a fanout of 1:16. The XRK39653's reference input accepts a LVPECL clock source. For normal operation (PLL used to source the outputs), the feedback output (QFB) is connected to the feedback input (FB_IN). The VCO range of operation is 200 to 500MHz. This means that the input/output ranges are determined by the divider setting. If /4 is used, the input/output range is 50 to 125MHz (high range), if /8 is used the input/output range is 25 to 62.5MHz (low range). For testing purposes two PLL bypass modes are provided. The first simply replaces the PLL output with the reference clock (PLL_EN=0, BYPASS=1). The dividers are still in
use. The second is a full bypass mode that has the PLL and divider operation removed (BYPASS=0). In this mode the reference clock directly sources the outputs drivers.
FEATURES
* * * *
8 LVCMOS Clock Outputs 1 Feedback Output LVPECL reference clock input 25-125 MHz input/output frequency range Input/Output range (/4): 50-125MHz Input/Output range (/8): 25-62.5MHz
* 150ps max output to output skew * Two bypass test mode options * * * * *
Fully Integrated PLL 3.3V Operation Pin compatible with MPC9653 Industrial temp range: -40C to +85C 32-Lead TQFP Packaging
FIGURE 1. BLOCK DIAGRAM OF THE XRK39653
VDD
QFB 0 0 1 /2 1 /4 1 Q0 0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
PECL PECL FB_IN
Ref
PLL
VDD
FB
PLL_EN VCO_SEL BYPASS
OE
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRK39653 3.3V, 8-OUTPUT ZERO DELAY BUFFER
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER XRK39653CQ XRK39653IQ PACKAGE TYPE 32-Lead TQFP 32-Lead TQFP
OPERATING TEMPERATURE RANGE 0C to +70C -40C to +85C
FIGURE 2. PIN OUT OF THE XRK39653
VCO_SEL
BYPASS
PLL_EN
GND
32 AVDD FB_IN NC NC NC NC AGND PECL 1 2 3 4 5 6 7 8 9
31
30
29
28
27
26
25 24 23 22 Q1 VDD Q2 GND Q3 VDD Q4 GND
GND
VDD
QFB
Q0
XRK39653
21 20 19 18 17
10
11
12
13
14
15
16
PECL
GND
VDD
VDD
OE
Q7
Q6
2
Q5
rx
REV. 1.0.0
rx
REV. 1.0.0
XRK39653 3.3V, 8-OUTPUT ZERO DELAY BUFFER
PIN DESCRIPTIONS
NUMBER 1 2 NAME AVDD FB_IN NC AGND PECL PECL OE VDD Q[7:0] Power Input Input Input Power Output pull-down PLL ground LVPECL - pos differential reference clock LVPECL - neg differential reference clock Output enable/disable and device reset Power supply Clock outputs Power Input pull-up TYPE Power supply for PLL External PLL feedback clock input DESCRIPTION
3, 4, 5, 6 7 8 9 10 11,15, 19, 23, 27, 12, 14, 16, 18, 20, 22, 24, 26 13, 17, 21, 25, 29 28 30 31 32
GND QFB PLL_EN BYPASS VCO_SEL
Power Output Input Input Input pull-up pull-up pull-up
Ground Feedback output for PLL PLL enable/disable select PLL and output divider bypass select VCO divider select
TABLE 1: CONTROL INPUT FUNCTION TABLE
Pin Name VCO_SEL PLL_EN 0 System Divide = 4 of VCO output PLL is bypassed and disabled. The PECL clock reference source drives the outputs through the divider blocks Complete bypass of the PLL and divider blocks. PECL reference clocks the outputs. Outputs enabled 1 System Divide = 8 of VCO output PLL enabled. Normal operation. VCO output drives the outputs through the divider blocks Normal operation. Dividers selected. Outputs tri-stated and device reset. VCO running at minimum frequency Default 1 1
BYPASS OE
1 0
3
XRK39653 3.3V, 8-OUTPUT ZERO DELAY BUFFER DC CHARACTERISTICS (VCC= 3.3 + 5%, TA= -40C TO +85C)
SYMBOL VCMRa VPP VIH VIL VOH VOL CHARACTERISTICS PECL Clock inputs common mode range PECL Clock peak-to-peak input voltage Input voltage high Input voltage low Output High Voltagea Output Low Voltagea 2.4 0.55 0.30 14-17 +200 5.0 10.0 10.0 VCC/2 MIN 1.0 300 2.0 TYP MAX VDD-0.6 1000 VDD+0.3 0.8 UNIT V mV V V V V V mA mA V
LVPECL LVPECL
LVCMOS LVCMOS IOH=-24mA IOL=24mA IOL=12mA
ZOUT IIN ICC_PLL ICCQ VTT
Output Impedance Input leakage current Maximum PLL supply current Maximum Quiescent supply current Output Termination Voltage
VIN =V DD or VIN =GND AVDD pin All VDD pins, OE=1
a. VCMR is the cross point of the differential input signal.
.
AC CHARACTERISTICS (VCC= 3.3 + 5%, TA= -40C TO +85C) a
SYMBOL fVCO fref VCO Frequency Input Reference Frequency /4 feedback /8 feedback PLL Bypass /4 feedback /8 feedback PARAMETER MIN 200 50 25 0 50 25 450 1.2 2 -75 125 TYP MAX 500 125 62.5 200 125 62.5 1000 VDD-0.75 UNIT MHz MHz PLL locked PLL locked bypass mode PLL locked PLL locked LVPECL LVPECL CONDITION
fMAX VPP VCMR tPW Min tSPO tPD
Max Output Frequency
MHz
PECL Clock peak-to-peak input voltage PECL input Common Mode range Input Reference Clock Minimum Pulse Width Propagation Delay - Static Phase Offset (PECL to FB_IN) Propagation Delay - PLL Bypassed Bypass mode 1 (BYPASS = 0) Bypass mode 2, (BYPASS = 1, PLL_EN = 0) Output-to-Output Skew Part to Part Skew (bypass PLL & divider) Cycle-to-Cycle Jitter
mV V ns ps
1.2 3.0
3.3 7.0 150 1.5 100
ns ns ps ns ps BYPASS=0
tskew(O) tskew(PP) tJIT(CC)
4
rx
REV. 1.0.0
CONDITION
PLL locked
rx
REV. 1.0.0
XRK39653 3.3V, 8-OUTPUT ZERO DELAY BUFFER
AC CHARACTERISTICS (VCC= 3.3 + 5%, TA= -40C TO +85C) a
SYMBOL tJIT(PER) tJIT(I/O) BW PARAMETER MIN TYP MAX 100 25 /4 feedback /8 feedback 45 50 0.8 - 4 0.5 - 1.3 55 10.0 100 1000 7 6 UNIT ps ps MHz MHz % ms ps ns ns 0.55 to 2.4V PLL locked CONDITION
Period Jitter I/O Phase Jitter (RMS) PLL bandwidth
DC tLOCK tor/tof tPLZ,HZ tPHZ,LZ
Output duty cycle Maximum PLL Lock Time Output Rise/Fall time Output Disable Time Output Enable Time
a. AC characteristics apply for parallel output termination of 50 to VTT.
MAXIMUM RATINGSa
SYMBOL VDD VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65
CHARACTERISTICS
MIN -0.3 -0.3 -0.3
MAX 3.9 VDD+0.3 VDD+0.3 +20 +50 125
UNIT V V V mA mA C
CONDITION
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability.
GENERAL SPECIFICATIONS
SYMBOL VTT MM HBM LU CIN CHARACTERISTICS Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) Latch-up immunity Input Capacitance 200 2000 200 4.0 MIN TYP VCC/2 MAX UNIT V V V mA pF Inputs CONDITION
5
XRK39653 3.3V, 8-OUTPUT ZERO DELAY BUFFER FIGURE 3. OUTPUT-TO-OUTPUT SKEW tSK(O)
VCC VCC/2 GND VCC VCC/2 GND tSK(O)
The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device.
FIGURE 4. PROPOGATION DELAY (t(O), STATIC PHASE OFFSET) TEST REFERENCE
VCC CCLKx VCC/2 GND VCC FB_IN VCC/2 GND t(O)
FIGURE 5. OUTPUT DUTY CYCLE (DC)
VCC VCC/2 tp T0 DC=tP/T0 x 100%
The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage
GND
FIGURE 6. I/O JITTER
CCLKx
FB_IN TJIT(I/O) = |T0-T1mean |
The deviation in t0 for a controlled edge with respect to a t 0 mean in a random sample of cycles
6
rx
REV. 1.0.0
rx
REV. 1.0.0
XRK39653 3.3V, 8-OUTPUT ZERO DELAY BUFFER
FIGURE 7. CYCLE-TO-CYCLE JITTER
TN
TN+1
TJIT(CC)= |TN-TN+1 |
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs
FIGURE 8. PERIOD JITTER
T0
TJIT(Per)= |TN-1/f0 |
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles
FIGURE 9. OUTPUT TRANSITION TIME TEST REFERENCE
VCC=3.3V 2.4 0.55 tof tor
7
XRK39653 3.3V, 8-OUTPUT ZERO DELAY BUFFER
PACKAGE DIMENSIONS
32 LEAD THIN QUAD FLAT PACK (7 x 7 x 1.4 mm TQFP) rev. 2.00
D D1 24 17
25
16
D1 32 9
D
1 B A2 e
8
C A Seating Plane A1 L
[
Note: The control dimension is the millimeter column INCHES SYMBOL MIN MAX MILLIMETERS MIN MAX
A A1 A2 B C D D1 e L
0.055 0.002 0.053 0.012 0.004 0.346 0.272
0.063 0.006 0.057 0.018 0.008 0.362 0.280
1.40 0.05 1.35 0.30 0.09 8.80 6.90
1.60 0.15 1.45 0.45 0.20 9.20 7.10
0.0315 BSC 0.018 0 0.030 7
0.80 BSC 0.45 0 0.75 7
8
rx
REV. 1.0.0
REVISION HISTORY
REVISION # DATE DESCRIPTION
rx
REV. 1.0.0
XRK39653 3.3V, 8-OUTPUT ZERO DELAY BUFFER
1.0.0
November 2006 Initial FINAL release.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2006 EXAR Corporation Datasheet November 2006. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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